The present invention relates to a semiconductor structure which includes an input buffer circuit.
Integrated circuits (IC""s) include input pads which receive external signals. Each input pad is typically connected to a corresponding input buffer circuit. FIG. 1 is a schematic diagram illustrating a typical input buffer circuit 100 which includes pull-up PMOS transistor 101, pull-down NMOS transistor 102, input pad 103 and internal input node 104. In response to the signal received on input pad 103, input buffer circuit 100 selectively connects internal input node 104 to a VCC voltage supply rail (i.e., a voltage supply rail which receives a first voltage, VCC, during normal operating conditions) or to a VSS voltage supply rail (i.e., a voltage supply rail which receives a second voltage, typically ground, during normal operating conditions).
Even if the VCC supply voltage has a voltage of 3.3 volts or less, it is desirable to allow a high input voltage (e.g., 5 volts) to be applied to input pad 103. However, when a high input voltage is applied to input pad 103, NMOS pull-down transistor 102 turns on. As a result, the source and drain of NMOS transistor 102 are each held at the Vss supply voltage (e.g., 0 volts), and the high input voltage is applied across the gate oxide of NMOS transistor 102. The high input voltage across the gate oxide of transistor 102 disadvantageously degrades the lifetime of the gate oxide of NMOS transistor 102.
One method used to solve this problem is to fabricate the gate oxide of each transistor on the IC to a thickness which is sufficient to withstand the applied high input voltage. However, such a thick oxide is typically not compatible with high speed advanced technology.
Another method is to form thick oxide transistors and thin oxide transistors on the same IC. Transistors required to receive high voltages are fabricated with a thick gate oxide. Conversely, transistors which are not required to receive high voltages are given a thin gate oxide to improve the speed of these transistors. However, this method disadvantageously increases process complexity.
It would therefore be desirable to have an input buffer circuit which is capable of receiving a high input voltage without experiencing degradation of gate oxide lifetime. It would further be desirable if such input buffer circuit does not reduce the operating speed of other transistors on the IC, or increase the complexity of the process used to fabricate the IC.
Accordingly, the present invention provides structures and methods for minimizing the voltage across the gate oxide of transistors used in input buffer circuits.
In one embodiment, the input buffer circuit includes a p-channel field effect transistor (FET) and a bias circuit. The p-channel FET has a source region coupled to the VCC voltage supply, a drain region coupled to the bias circuit, and a gate electrode coupled to receive the input voltage VIN. The bias circuit controls the voltage at the drain of the p-channel FET and provides an output signal which effectively transmits the input voltage signal VIN to the on-chip integrated circuitry.
When a high input voltage VIN is applied to the gate electrode of the p-channel FET, the bias circuit maintains the voltage at the drain region of the p-channel FET at a level which is slightly greater than the VSS supply voltage. As a result, the voltage across the gate oxide at the drain of the p-channel FET is reduced. The output signal provided by the bias circuit has a logic low level which is slightly greater than the VSS supply voltage. In one variation, the p-channel FET and the bias circuit form a current mirror circuit.
In another embodiment, the input buffer circuit includes an n-channel FET and a bias circuit. The n-channel transistor has a gate electrode coupled to receive the input voltage VIN, a drain region coupled to the VCC voltage supply, and a source region coupled to the bias circuit and to the output terminal of the input buffer circuit. When a logic high voltage is applied to the input terminal, the n-channel transistor turns on, thereby providing an output voltage which is approximately equal to the VCC supply voltage. When a logic low voltage is applied to the input terminal, the bias circuit maintains a low output voltage which is approximately equal to the VSS supply voltage. Consequently, the gate oxide of the n-channel transistor is not exposed to high voltages. The bias circuit can be, for example, a current source. In a particular embodiment, the n-channel FET and the bias circuit form a current mirror circuit.
The invention also includes a method of using a p-channel FET in an input buffer circuit. This method includes the steps of: (1) turning the p-channel transistor on in response to a logic low input voltage, (2) turning the p-channel transistor off in response to a logic high input voltage, and (3) biasing the drain region of the p-channel transistor at a bias voltage when a logic high input voltage is applied to the gate electrode of the p-channel transistor, the bias voltage being greater than the VSS supply voltage and less than the VCC supply voltage.
A method of using an n-channel FET in an input buffer circuit includes the steps of: (1) turning the n-channel transistor on in response to a logic high input voltage, (2) turning the n-channel transistor off in response to a logic low input voltage, and (3) biasing the source region of the n-channel transistor at a bias voltage when a logic low input voltage is applied to the gate electrode of said n-channel FET, the bias voltage being approximately equal to the VSS supply voltage.
The present invention will be more fully understood in view of the following detailed description taken together with the drawings.